Design And Reuse, The Web's System-On-Chip Design Resource

802.16e standard known as the Mobile Wimax standard integrates various coding schemes in the Physical layer specification including the most efficient ones, the LDPC. In this article we will present the physical layer baselines, we will then focus on the error correcting codes to finally detail our implementation.

Featured Demos

OpenSPARC T1 from Sun Microsystems- For the first time in history, developers gain access to the chip multi-threading (CMT) technology unique to the UltraSPARC T1 processor, which is released under the GNU General Public License (GPL).

xIDE toolkit from Cambridge Consultants - Download the xIDE Integrated Development Environments for our XAP 16- and 32-bit processors. These IDEs let you write programs in C or Assembler and compile and run them on the built-in XAP Instruction Set Simulator.

DP8051 pipelined 8-bit microcontroller from Digital Core Design

LA16 - Synthesizable HDL Core from Evatronix

ARChitect™ Processor Configuration Tool Demo from ARC International - See how easy it is to create your own processor

PLLXpert Online from Ceva enables a designer to either create a custom PLL or alternatively download an existing PLL reference design that can be fine-tuned by the designer for a specific application.

On-line Evaluation and Front-End view generation for a Single-Port RAM generator targeting TSMC - 0.25 um from Dolphin Integration

Super-FinSim, a complete simulation environment for Verilog from Fintronic USA Inc.

News

Top Story

Sun and Xilinx Ignite CMT Development Market With Introduction of Feature-Rich, High-Performance Programmable OpenSPARC Evaluation Platform

Industry leaders join forces to combine industry's first 64-bit open-source multi-core, multi-threaded microprocessor with industry-leading 65nm Virtex-5 high-performance FPGA

Webcast / Podcast

Featured Webcast

Achieving Maximum Reuse Leverage: Lessons from benchmarking 1000+ IC projects

Great Expectations probably describes the feeling prevalent throughout the semiconductor industry when reuse first entered the IC design paradigm more than ten years ago. Reuse was supposed to unleash huge boosts in development productivity and output that would offset the Design Productivity Gap. Has it happened? If not, why not?

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Integrating Nonvolatile Memory in SoC Designs: Save Time and Reduce Design Costs (Jan. 23, 2007)

The role of virtual fabless providers for a predictable road to product (Jan. 2, 2007)

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